/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_WUGENMPU_H_
#define CSLR_WUGENMPU_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 WKG_CONTROL_0;
    volatile Uint8  RSVD0[12];
    volatile Uint32 WKG_ENB_A_0;
    volatile Uint32 WKG_ENB_B_0;
    volatile Uint32 WKG_ENB_C_0;
    volatile Uint32 WKG_ENB_D_0;
    volatile Uint32 WKG_ENB_E_0;
    volatile Uint32 WKG_ENB_SECURE_A_0;
    volatile Uint32 WKG_ENB_SECURE_B_0;
    volatile Uint32 WKG_ENB_SECURE_C_0;
    volatile Uint32 WKG_ENB_SECURE_D_0;
    volatile Uint32 WKG_ENB_SECURE_E_0;
    volatile Uint8  RSVD1[968];
    volatile Uint32 WKG_CONTROL_1;
    volatile Uint8  RSVD2[12];
    volatile Uint32 WKG_ENB_A_1;
    volatile Uint32 WKG_ENB_B_1;
    volatile Uint32 WKG_ENB_C_1;
    volatile Uint32 WKG_ENB_D_1;
    volatile Uint32 WKG_ENB_E_1;
    volatile Uint32 WKG_ENB_SECURE_A_1;
    volatile Uint32 WKG_ENB_SECURE_B_1;
    volatile Uint32 WKG_ENB_SECURE_C_1;
    volatile Uint32 WKG_ENB_SECURE_D_1;
    volatile Uint32 WKG_ENB_SECURE_E_1;
    volatile Uint8  RSVD3[968];
    volatile Uint32 AUX_CORE_BOOT_0;
    volatile Uint32 AUX_CORE_BOOT_1;
    volatile Uint32 STM_HWEVENTS_INV;
    volatile Uint32 AMBA_IF_MODE;
    volatile Uint8  RSVD4[1008];
    volatile Uint32 PTMSYNCREQ_MASK;
    volatile Uint32 PTMSYNCREQ_EN;
    volatile Uint32 TIMESTAMPCYCLELO;
    volatile Uint32 TIMESTAMPCYCLEHI;
} CSL_WugenMpuRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* WakeUpGen Control and Status Register for CPU0 */
#define CSL_WUGENMPU_WKG_CONTROL_0                              (0x0U)

/* WKG_ENB_A_0 */
#define CSL_WUGENMPU_WKG_ENB_A_0                                (0x10U)

/* WKG_ENB_B_0 */
#define CSL_WUGENMPU_WKG_ENB_B_0                                (0x14U)

/* WKG_ENB_C_0 */
#define CSL_WUGENMPU_WKG_ENB_C_0                                (0x18U)

/* WKG_ENB_D_0 */
#define CSL_WUGENMPU_WKG_ENB_D_0                                (0x1CU)

/* WKG_ENB_E_0 */
#define CSL_WUGENMPU_WKG_ENB_E_0                                (0x20U)

/* WKG_ENB_SECURE_A_0 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0                         (0x24U)

/* WKG_ENB_SECURE_B_0 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0                         (0x28U)

/* WKG_ENB_SECURE_C_0 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0                         (0x2CU)

/* WKG_ENB_SECURE_D_0 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0                         (0x30U)

/* WKG_ENB_SECURE_E_0 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0                         (0x34U)

/* WakeUpGen Control and Status Register for CPU1 */
#define CSL_WUGENMPU_WKG_CONTROL_1                              (0x400U)

/* WKG_ENB_A_1 */
#define CSL_WUGENMPU_WKG_ENB_A_1                                (0x410U)

/* WKG_ENB_B_1 */
#define CSL_WUGENMPU_WKG_ENB_B_1                                (0x414U)

/* WKG_ENB_C_1 */
#define CSL_WUGENMPU_WKG_ENB_C_1                                (0x418U)

/* WKG_ENB_D_1 */
#define CSL_WUGENMPU_WKG_ENB_D_1                                (0x41CU)

/* WKG_ENB_E_1 */
#define CSL_WUGENMPU_WKG_ENB_E_1                                (0x420U)

/* WKG_ENB_SECURE_A_1 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1                         (0x424U)

/* WKG_ENB_SECURE_B_1 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1                         (0x428U)

/* WKG_ENB_SECURE_C_1 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1                         (0x42CU)

/* WKG_ENB_SECURE_D_1 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1                         (0x430U)

/* WKG_ENB_SECURE_E_1 */
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1                         (0x434U)

/* AUX_CORE_BOOT_0 */
#define CSL_WUGENMPU_AUX_CORE_BOOT_0                            (0x800U)

/* AUX_CORE_BOOT_1 */
#define CSL_WUGENMPU_AUX_CORE_BOOT_1                            (0x804U)

/* to give programmable control of inverting or not inverting PO_HW_DBG_OUT
 * going to HWEVENTS[31:0] input of STM */
#define CSL_WUGENMPU_STM_HWEVENTS_INV                           (0x808U)

/* The AMBA_IF_MODE register controls the eagle interface tieoff values for
 * BI,BO,BCM and SBD. It also has APB_FENCE_DIS which can be used to disable
 * the APB fencing logic and get same behavior as in OMAP4. This register is
 * located in MPU AON domain and is reset by MPU_AON_RSTN. */
#define CSL_WUGENMPU_AMBA_IF_MODE                               (0x80CU)

/* PTMSYNCREQ_MASK */
#define CSL_WUGENMPU_PTMSYNCREQ_MASK                            (0xC00U)

/* PTMSYNCREQ_EN */
#define CSL_WUGENMPU_PTMSYNCREQ_EN                              (0xC04U)

/* TIMESTAMPCYCLELO */
#define CSL_WUGENMPU_TIMESTAMPCYCLELO                           (0xC08U)

/* TIMESTAMPCYCLEHI */
#define CSL_WUGENMPU_TIMESTAMPCYCLEHI                           (0xC0CU)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* WKG_CONTROL_0 */

#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFI_MASK              (0x00000100U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFI_SHIFT             (8U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFI_RESETVAL          (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFI_MAX               (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFE_MASK              (0x00000200U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFE_SHIFT             (9U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFE_RESETVAL          (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_STANDBYWFE_MAX               (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_EVENTO_MASK                  (0x00000400U)
#define CSL_WUGENMPU_WKG_CONTROL_0_EVENTO_SHIFT                 (10U)
#define CSL_WUGENMPU_WKG_CONTROL_0_EVENTO_RESETVAL              (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_EVENTO_MAX                   (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_COLD_RESET_MASK          (0x00002000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_COLD_RESET_SHIFT         (13U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_COLD_RESET_RESETVAL      (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_COLD_RESET_MAX           (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_WARM_RESET_MASK          (0x00004000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_WARM_RESET_SHIFT         (14U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_WARM_RESET_RESETVAL      (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_MPU_WARM_RESET_MAX           (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_DOMAINRESET_MASK             (0x00008000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_DOMAINRESET_SHIFT            (15U)
#define CSL_WUGENMPU_WKG_CONTROL_0_DOMAINRESET_RESETVAL         (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_0_DOMAINRESET_MAX              (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_0_RESETVAL                     (0x00000000U)

/* WKG_ENB_A_0 */

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_MASK         (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_SHIFT        (0U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_MASK         (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_SHIFT        (1U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_MASK         (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_SHIFT        (2U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_MASK         (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_SHIFT        (3U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_MASK         (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_SHIFT        (4U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_MASK         (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_SHIFT        (5U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_MASK         (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_SHIFT        (6U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_MASK         (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_SHIFT        (7U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_MASK         (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_SHIFT        (8U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_RESETVAL     (0x00000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_MASK         (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_SHIFT        (9U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_0_RESETVAL                       (0xfffffeffU)

/* WKG_ENB_B_0 */

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_MASK        (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_SHIFT       (4U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_MASK        (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_SHIFT       (5U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_MASK        (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_SHIFT       (6U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_MASK        (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_SHIFT       (7U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_MASK        (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_SHIFT       (8U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_MASK        (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_SHIFT       (9U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_0_RESETVAL                       (0xffffffffU)

/* WKG_ENB_C_0 */

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_MASK        (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_SHIFT       (4U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_MASK        (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_SHIFT       (5U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_MASK        (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_SHIFT       (6U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_MASK        (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_SHIFT       (7U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_MASK        (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_SHIFT       (8U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_MASK        (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_SHIFT       (9U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_0_RESETVAL                       (0xffffffffU)

/* WKG_ENB_D_0 */

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_MASK       (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_SHIFT      (4U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_MASK       (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_SHIFT      (5U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_MASK       (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_SHIFT      (6U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_MASK       (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_SHIFT      (7U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_MASK       (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_SHIFT      (8U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_MASK       (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_SHIFT      (9U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_MASK       (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_SHIFT      (10U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_MASK       (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_SHIFT      (11U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_MASK       (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_SHIFT      (12U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_MASK       (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_SHIFT      (13U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_MASK       (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_SHIFT      (14U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_MASK       (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_SHIFT      (15U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_MASK       (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_SHIFT      (16U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_MASK       (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_SHIFT      (17U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_MASK       (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_SHIFT      (18U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_MASK       (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_SHIFT      (19U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_MASK       (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_SHIFT      (20U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_MASK       (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_SHIFT      (21U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_MASK       (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_SHIFT      (22U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_MASK       (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_SHIFT      (23U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_MASK       (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_SHIFT      (24U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_MASK       (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_SHIFT      (25U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_MASK       (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_SHIFT      (26U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_MASK       (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_SHIFT      (27U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_MASK       (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_SHIFT      (28U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_MASK       (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_SHIFT      (29U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_MASK       (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_SHIFT      (30U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_MASK       (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_SHIFT      (31U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_0_RESETVAL                       (0xffffffffU)

/* WKG_ENB_E_0 */

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_MASK       (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_SHIFT      (0U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_MASK       (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_SHIFT      (1U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_MASK       (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_SHIFT      (2U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_MASK       (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_SHIFT      (3U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_MASK       (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_SHIFT      (4U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_MASK       (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_SHIFT      (5U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_MASK       (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_SHIFT      (6U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_MASK       (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_SHIFT      (7U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_MASK       (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_SHIFT      (8U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_MASK       (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_SHIFT      (9U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_MASK       (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_SHIFT      (10U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_MASK       (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_SHIFT      (11U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_MASK       (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_SHIFT      (12U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_MASK       (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_SHIFT      (13U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_MASK       (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_SHIFT      (14U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_MASK       (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_SHIFT      (15U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_MASK       (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_SHIFT      (16U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_MASK       (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_SHIFT      (17U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_MASK       (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_SHIFT      (18U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_MASK       (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_SHIFT      (19U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_MASK       (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_SHIFT      (20U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_MASK       (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_SHIFT      (21U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_MASK       (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_SHIFT      (22U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_MASK       (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_SHIFT      (23U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_MASK       (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_SHIFT      (24U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_MASK       (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_SHIFT      (25U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_MASK       (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_SHIFT      (26U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_MASK       (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_SHIFT      (27U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_MASK       (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_SHIFT      (28U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_MASK       (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_SHIFT      (29U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_MASK       (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_SHIFT      (30U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_MASK       (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_SHIFT      (31U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_0_RESETVAL                       (0xffffffffU)

/* WKG_ENB_SECURE_A_0 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR0_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR0_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR0_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR0_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR1_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR1_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR1_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR1_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR2_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR2_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR2_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR2_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR3_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR3_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR3_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR3_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR4_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR4_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR4_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR4_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR5_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR5_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR5_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR5_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR6_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR6_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR6_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR6_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR7_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR7_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR7_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR7_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR8_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR8_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR8_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR8_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR9_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR9_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR9_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR9_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR10_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR10_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR10_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR10_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR11_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR11_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR11_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR11_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR12_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR12_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR12_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR12_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR13_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR13_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR13_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR13_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR14_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR14_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR14_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR14_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR15_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR15_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR15_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR15_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR16_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR16_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR16_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR16_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR17_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR17_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR17_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR17_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR18_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR18_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR18_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR18_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR19_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR19_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR19_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR19_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR20_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR20_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR20_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR20_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR21_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR21_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR21_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR21_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR22_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR22_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR22_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR22_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR23_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR23_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR23_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR23_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR24_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR24_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR24_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR24_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR25_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR25_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR25_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR25_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR26_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR26_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR26_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR26_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR27_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR27_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR27_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR27_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR28_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR28_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR28_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR28_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR29_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR29_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR29_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR29_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR30_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR30_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR30_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR30_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR31_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR31_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR31_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_WKG_ENB_SECURE_FOR_INTR31_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_0_RESETVAL                (0xfffffeffU)

/* WKG_ENB_SECURE_B_0 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR32_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR32_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR32_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR32_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR33_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR33_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR33_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR33_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR34_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR34_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR34_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR34_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR35_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR35_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR35_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR35_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR36_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR36_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR36_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR36_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR37_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR37_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR37_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR37_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR38_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR38_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR38_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR38_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR39_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR39_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR39_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR39_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR40_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR40_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR40_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR40_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR41_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR41_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR41_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR41_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR42_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR42_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR42_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR42_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR43_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR43_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR43_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR43_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR44_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR44_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR44_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR44_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR45_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR45_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR45_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR45_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR46_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR46_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR46_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR46_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR47_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR47_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR47_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR47_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR48_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR48_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR48_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR48_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR49_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR49_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR49_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR49_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR50_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR50_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR50_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR50_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR51_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR51_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR51_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR51_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR52_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR52_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR52_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR52_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR53_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR53_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR53_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR53_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR54_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR54_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR54_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR54_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR55_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR55_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR55_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR55_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR56_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR56_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR56_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR56_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR57_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR57_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR57_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR57_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR58_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR58_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR58_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR58_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR59_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR59_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR59_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR59_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR60_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR60_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR60_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR60_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR61_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR61_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR61_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR61_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR62_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR62_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR62_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR62_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR63_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR63_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR63_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_WKG_ENB_SECURE_FOR_INTR63_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_0_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_C_0 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR64_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR64_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR64_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR64_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR65_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR65_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR65_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR65_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR66_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR66_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR66_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR66_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR67_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR67_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR67_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR67_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR68_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR68_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR68_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR68_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR69_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR69_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR69_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR69_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR70_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR70_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR70_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR70_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR71_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR71_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR71_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR71_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR72_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR72_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR72_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR72_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR73_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR73_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR73_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR73_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR74_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR74_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR74_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR74_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR75_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR75_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR75_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR75_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR76_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR76_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR76_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR76_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR77_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR77_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR77_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR77_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR78_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR78_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR78_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR78_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR79_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR79_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR79_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR79_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR80_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR80_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR80_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR80_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR81_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR81_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR81_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR81_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR82_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR82_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR82_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR82_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR83_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR83_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR83_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR83_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR84_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR84_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR84_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR84_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR85_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR85_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR85_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR85_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR86_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR86_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR86_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR86_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR87_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR87_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR87_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR87_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR88_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR88_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR88_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR88_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR89_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR89_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR89_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR89_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR90_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR90_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR90_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR90_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR91_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR91_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR91_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR91_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR92_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR92_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR92_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR92_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR93_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR93_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR93_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR93_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR94_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR94_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR94_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR94_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR95_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR95_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR95_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_WKG_ENB_SECURE_FOR_INTR95_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_0_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_D_0 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR96_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR96_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR96_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR96_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR97_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR97_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR97_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR97_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR98_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR98_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR98_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR98_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR99_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR99_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR99_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR99_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR100_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR100_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR100_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR100_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR101_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR101_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR101_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR101_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR102_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR102_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR102_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR102_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR103_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR103_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR103_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR103_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR104_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR104_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR104_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR104_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR105_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR105_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR105_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR105_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR106_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR106_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR106_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR106_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR107_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR107_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR107_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR107_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR108_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR108_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR108_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR108_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR109_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR109_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR109_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR109_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR110_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR110_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR110_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR110_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR111_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR111_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR111_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR111_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR112_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR112_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR112_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR112_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR113_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR113_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR113_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR113_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR114_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR114_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR114_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR114_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR115_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR115_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR115_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR115_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR116_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR116_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR116_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR116_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR117_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR117_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR117_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR117_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR118_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR118_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR118_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR118_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR119_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR119_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR119_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR119_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR120_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR120_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR120_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR120_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR121_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR121_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR121_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR121_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR122_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR122_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR122_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR122_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR123_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR123_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR123_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR123_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR124_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR124_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR124_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR124_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR125_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR125_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR125_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR125_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR126_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR126_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR126_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR126_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR127_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR127_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR127_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_WKG_ENB_SECURE_FOR_INTR127_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_0_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_E_0 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR128_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR128_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR128_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR128_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR129_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR129_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR129_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR129_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR130_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR130_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR130_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR130_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR131_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR131_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR131_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR131_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR132_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR132_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR132_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR132_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR133_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR133_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR133_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR133_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR134_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR134_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR134_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR134_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR135_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR135_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR135_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR135_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR136_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR136_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR136_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR136_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR137_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR137_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR137_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR137_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR138_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR138_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR138_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR138_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR139_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR139_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR139_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR139_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR140_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR140_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR140_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR140_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR141_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR141_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR141_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR141_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR142_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR142_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR142_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR142_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR143_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR143_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR143_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR143_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR144_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR144_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR144_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR144_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR145_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR145_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR145_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR145_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR146_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR146_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR146_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR146_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR147_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR147_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR147_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR147_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR148_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR148_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR148_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR148_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR149_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR149_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR149_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR149_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR150_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR150_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR150_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR150_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR151_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR151_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR151_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR151_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR152_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR152_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR152_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR152_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR153_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR153_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR153_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR153_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR154_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR154_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR154_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR154_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR155_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR155_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR155_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR155_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR156_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR156_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR156_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR156_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR157_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR157_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR157_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR157_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR158_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR158_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR158_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR158_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR159_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR159_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR159_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_WKG_ENB_SECURE_FOR_INTR159_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_0_RESETVAL                (0xffffffffU)

/* WKG_CONTROL_1 */

#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFI_MASK              (0x00000100U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFI_SHIFT             (8U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFI_RESETVAL          (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFI_MAX               (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFE_MASK              (0x00000200U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFE_SHIFT             (9U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFE_RESETVAL          (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_STANDBYWFE_MAX               (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_EVENTO_MASK                  (0x00000400U)
#define CSL_WUGENMPU_WKG_CONTROL_1_EVENTO_SHIFT                 (10U)
#define CSL_WUGENMPU_WKG_CONTROL_1_EVENTO_RESETVAL              (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_EVENTO_MAX                   (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_COLD_RESET_MASK          (0x00002000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_COLD_RESET_SHIFT         (13U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_COLD_RESET_RESETVAL      (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_COLD_RESET_MAX           (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_WARM_RESET_MASK          (0x00004000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_WARM_RESET_SHIFT         (14U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_WARM_RESET_RESETVAL      (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_MPU_WARM_RESET_MAX           (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_DOMAINRESET_MASK             (0x00008000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_DOMAINRESET_SHIFT            (15U)
#define CSL_WUGENMPU_WKG_CONTROL_1_DOMAINRESET_RESETVAL         (0x00000000U)
#define CSL_WUGENMPU_WKG_CONTROL_1_DOMAINRESET_MAX              (0x00000001U)

#define CSL_WUGENMPU_WKG_CONTROL_1_RESETVAL                     (0x00000000U)

/* WKG_ENB_A_1 */

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_MASK         (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_SHIFT        (0U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_MASK         (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_SHIFT        (1U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_MASK         (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_SHIFT        (2U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_MASK         (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_SHIFT        (3U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_MASK         (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_SHIFT        (4U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_MASK         (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_SHIFT        (5U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_MASK         (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_SHIFT        (6U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_MASK         (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_SHIFT        (7U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_MASK         (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_SHIFT        (8U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_RESETVAL     (0x00000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_MASK         (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_SHIFT        (9U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_RESETVAL     (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_MAX          (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_A_1_RESETVAL                       (0xfffffeffU)

/* WKG_ENB_B_1 */

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_MASK        (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_SHIFT       (4U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_MASK        (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_SHIFT       (5U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_MASK        (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_SHIFT       (6U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_MASK        (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_SHIFT       (7U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_MASK        (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_SHIFT       (8U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_MASK        (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_SHIFT       (9U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_B_1_RESETVAL                       (0xffffffffU)

/* WKG_ENB_C_1 */

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_MASK        (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_SHIFT       (4U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_MASK        (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_SHIFT       (5U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_MASK        (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_SHIFT       (6U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_MASK        (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_SHIFT       (7U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_MASK        (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_SHIFT       (8U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_MASK        (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_SHIFT       (9U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_MASK        (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_SHIFT       (10U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_MASK        (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_SHIFT       (11U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_MASK        (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_SHIFT       (12U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_MASK        (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_SHIFT       (13U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_MASK        (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_SHIFT       (14U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_MASK        (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_SHIFT       (15U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_MASK        (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_SHIFT       (16U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_MASK        (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_SHIFT       (17U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_MASK        (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_SHIFT       (18U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_MASK        (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_SHIFT       (19U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_MASK        (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_SHIFT       (20U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_MASK        (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_SHIFT       (21U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_MASK        (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_SHIFT       (22U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_MASK        (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_SHIFT       (23U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_MASK        (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_SHIFT       (24U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_MASK        (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_SHIFT       (25U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_MASK        (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_SHIFT       (26U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_MASK        (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_SHIFT       (27U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_MASK        (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_SHIFT       (28U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_MASK        (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_SHIFT       (29U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_MASK        (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_SHIFT       (30U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_MASK        (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_SHIFT       (31U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_C_1_RESETVAL                       (0xffffffffU)

/* WKG_ENB_D_1 */

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_MASK        (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_SHIFT       (0U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_MASK        (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_SHIFT       (1U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_MASK        (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_SHIFT       (2U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_MASK        (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_SHIFT       (3U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_RESETVAL    (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_MAX         (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_MASK       (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_SHIFT      (4U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_MASK       (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_SHIFT      (5U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_MASK       (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_SHIFT      (6U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_MASK       (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_SHIFT      (7U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_MASK       (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_SHIFT      (8U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_MASK       (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_SHIFT      (9U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_MASK       (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_SHIFT      (10U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_MASK       (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_SHIFT      (11U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_MASK       (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_SHIFT      (12U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_MASK       (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_SHIFT      (13U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_MASK       (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_SHIFT      (14U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_MASK       (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_SHIFT      (15U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_MASK       (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_SHIFT      (16U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_MASK       (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_SHIFT      (17U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_MASK       (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_SHIFT      (18U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_MASK       (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_SHIFT      (19U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_MASK       (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_SHIFT      (20U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_MASK       (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_SHIFT      (21U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_MASK       (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_SHIFT      (22U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_MASK       (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_SHIFT      (23U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_MASK       (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_SHIFT      (24U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_MASK       (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_SHIFT      (25U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_MASK       (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_SHIFT      (26U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_MASK       (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_SHIFT      (27U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_MASK       (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_SHIFT      (28U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_MASK       (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_SHIFT      (29U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_MASK       (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_SHIFT      (30U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_MASK       (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_SHIFT      (31U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_D_1_RESETVAL                       (0xffffffffU)

/* WKG_ENB_E_1 */

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_MASK       (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_SHIFT      (0U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_MASK       (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_SHIFT      (1U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_MASK       (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_SHIFT      (2U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_MASK       (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_SHIFT      (3U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_MASK       (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_SHIFT      (4U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_MASK       (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_SHIFT      (5U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_MASK       (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_SHIFT      (6U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_MASK       (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_SHIFT      (7U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_MASK       (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_SHIFT      (8U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_MASK       (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_SHIFT      (9U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_MASK       (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_SHIFT      (10U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_MASK       (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_SHIFT      (11U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_MASK       (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_SHIFT      (12U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_MASK       (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_SHIFT      (13U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_MASK       (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_SHIFT      (14U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_MASK       (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_SHIFT      (15U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_MASK       (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_SHIFT      (16U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_MASK       (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_SHIFT      (17U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_MASK       (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_SHIFT      (18U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_MASK       (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_SHIFT      (19U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_MASK       (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_SHIFT      (20U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_MASK       (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_SHIFT      (21U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_MASK       (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_SHIFT      (22U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_MASK       (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_SHIFT      (23U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_MASK       (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_SHIFT      (24U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_MASK       (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_SHIFT      (25U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_MASK       (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_SHIFT      (26U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_MASK       (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_SHIFT      (27U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_MASK       (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_SHIFT      (28U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_MASK       (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_SHIFT      (29U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_MASK       (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_SHIFT      (30U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_MASK       (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_SHIFT      (31U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_RESETVAL   (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_MAX        (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_E_1_RESETVAL                       (0xffffffffU)

/* WKG_ENB_SECURE_A_1 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR0_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR0_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR0_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR0_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR1_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR1_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR1_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR1_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR2_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR2_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR2_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR2_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR3_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR3_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR3_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR3_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR4_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR4_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR4_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR4_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR5_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR5_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR5_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR5_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR6_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR6_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR6_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR6_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR7_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR7_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR7_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR7_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR8_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR8_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR8_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR8_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR9_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR9_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR9_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR9_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR10_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR10_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR10_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR10_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR11_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR11_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR11_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR11_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR12_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR12_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR12_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR12_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR13_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR13_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR13_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR13_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR14_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR14_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR14_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR14_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR15_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR15_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR15_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR15_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR16_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR16_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR16_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR16_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR17_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR17_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR17_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR17_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR18_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR18_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR18_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR18_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR19_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR19_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR19_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR19_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR20_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR20_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR20_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR20_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR21_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR21_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR21_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR21_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR22_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR22_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR22_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR22_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR23_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR23_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR23_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR23_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR24_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR24_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR24_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR24_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR25_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR25_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR25_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR25_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR26_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR26_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR26_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR26_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR27_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR27_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR27_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR27_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR28_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR28_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR28_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR28_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR29_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR29_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR29_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR29_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR30_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR30_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR30_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR30_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR31_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR31_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR31_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_WKG_ENB_SECURE_FOR_INTR31_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_A_1_RESETVAL                (0xfffffeffU)

/* WKG_ENB_SECURE_B_1 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR32_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR32_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR32_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR32_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR33_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR33_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR33_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR33_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR34_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR34_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR34_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR34_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR35_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR35_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR35_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR35_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR36_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR36_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR36_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR36_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR37_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR37_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR37_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR37_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR38_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR38_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR38_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR38_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR39_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR39_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR39_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR39_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR40_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR40_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR40_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR40_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR41_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR41_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR41_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR41_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR42_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR42_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR42_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR42_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR43_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR43_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR43_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR43_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR44_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR44_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR44_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR44_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR45_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR45_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR45_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR45_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR46_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR46_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR46_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR46_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR47_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR47_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR47_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR47_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR48_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR48_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR48_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR48_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR49_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR49_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR49_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR49_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR50_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR50_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR50_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR50_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR51_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR51_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR51_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR51_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR52_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR52_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR52_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR52_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR53_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR53_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR53_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR53_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR54_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR54_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR54_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR54_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR55_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR55_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR55_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR55_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR56_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR56_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR56_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR56_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR57_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR57_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR57_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR57_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR58_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR58_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR58_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR58_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR59_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR59_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR59_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR59_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR60_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR60_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR60_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR60_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR61_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR61_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR61_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR61_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR62_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR62_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR62_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR62_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR63_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR63_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR63_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_WKG_ENB_SECURE_FOR_INTR63_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_B_1_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_C_1 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR64_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR64_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR64_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR64_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR65_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR65_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR65_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR65_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR66_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR66_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR66_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR66_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR67_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR67_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR67_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR67_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR68_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR68_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR68_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR68_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR69_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR69_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR69_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR69_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR70_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR70_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR70_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR70_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR71_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR71_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR71_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR71_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR72_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR72_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR72_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR72_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR73_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR73_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR73_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR73_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR74_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR74_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR74_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR74_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR75_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR75_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR75_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR75_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR76_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR76_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR76_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR76_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR77_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR77_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR77_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR77_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR78_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR78_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR78_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR78_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR79_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR79_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR79_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR79_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR80_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR80_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR80_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR80_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR81_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR81_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR81_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR81_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR82_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR82_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR82_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR82_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR83_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR83_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR83_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR83_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR84_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR84_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR84_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR84_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR85_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR85_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR85_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR85_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR86_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR86_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR86_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR86_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR87_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR87_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR87_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR87_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR88_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR88_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR88_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR88_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR89_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR89_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR89_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR89_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR90_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR90_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR90_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR90_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR91_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR91_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR91_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR91_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR92_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR92_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR92_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR92_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR93_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR93_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR93_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR93_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR94_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR94_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR94_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR94_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR95_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR95_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR95_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_WKG_ENB_SECURE_FOR_INTR95_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_C_1_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_D_1 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR96_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR96_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR96_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR96_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR97_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR97_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR97_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR97_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR98_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR98_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR98_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR98_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR99_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR99_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR99_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR99_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR100_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR100_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR100_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR100_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR101_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR101_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR101_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR101_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR102_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR102_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR102_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR102_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR103_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR103_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR103_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR103_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR104_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR104_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR104_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR104_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR105_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR105_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR105_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR105_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR106_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR106_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR106_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR106_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR107_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR107_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR107_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR107_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR108_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR108_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR108_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR108_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR109_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR109_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR109_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR109_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR110_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR110_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR110_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR110_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR111_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR111_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR111_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR111_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR112_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR112_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR112_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR112_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR113_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR113_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR113_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR113_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR114_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR114_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR114_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR114_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR115_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR115_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR115_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR115_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR116_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR116_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR116_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR116_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR117_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR117_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR117_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR117_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR118_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR118_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR118_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR118_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR119_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR119_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR119_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR119_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR120_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR120_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR120_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR120_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR121_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR121_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR121_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR121_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR122_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR122_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR122_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR122_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR123_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR123_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR123_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR123_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR124_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR124_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR124_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR124_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR125_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR125_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR125_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR125_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR126_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR126_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR126_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR126_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR127_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR127_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR127_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_WKG_ENB_SECURE_FOR_INTR127_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_D_1_RESETVAL                (0xffffffffU)

/* WKG_ENB_SECURE_E_1 */

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR128_MASK  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR128_SHIFT  (0U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR128_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR128_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR129_MASK  (0x00000002U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR129_SHIFT  (1U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR129_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR129_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR130_MASK  (0x00000004U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR130_SHIFT  (2U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR130_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR130_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR131_MASK  (0x00000008U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR131_SHIFT  (3U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR131_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR131_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR132_MASK  (0x00000010U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR132_SHIFT  (4U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR132_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR132_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR133_MASK  (0x00000020U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR133_SHIFT  (5U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR133_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR133_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR134_MASK  (0x00000040U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR134_SHIFT  (6U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR134_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR134_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR135_MASK  (0x00000080U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR135_SHIFT  (7U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR135_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR135_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR136_MASK  (0x00000100U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR136_SHIFT  (8U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR136_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR136_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR137_MASK  (0x00000200U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR137_SHIFT  (9U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR137_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR137_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR138_MASK  (0x00000400U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR138_SHIFT  (10U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR138_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR138_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR139_MASK  (0x00000800U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR139_SHIFT  (11U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR139_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR139_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR140_MASK  (0x00001000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR140_SHIFT  (12U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR140_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR140_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR141_MASK  (0x00002000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR141_SHIFT  (13U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR141_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR141_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR142_MASK  (0x00004000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR142_SHIFT  (14U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR142_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR142_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR143_MASK  (0x00008000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR143_SHIFT  (15U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR143_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR143_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR144_MASK  (0x00010000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR144_SHIFT  (16U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR144_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR144_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR145_MASK  (0x00020000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR145_SHIFT  (17U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR145_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR145_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR146_MASK  (0x00040000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR146_SHIFT  (18U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR146_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR146_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR147_MASK  (0x00080000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR147_SHIFT  (19U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR147_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR147_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR148_MASK  (0x00100000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR148_SHIFT  (20U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR148_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR148_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR149_MASK  (0x00200000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR149_SHIFT  (21U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR149_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR149_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR150_MASK  (0x00400000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR150_SHIFT  (22U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR150_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR150_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR151_MASK  (0x00800000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR151_SHIFT  (23U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR151_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR151_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR152_MASK  (0x01000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR152_SHIFT  (24U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR152_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR152_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR153_MASK  (0x02000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR153_SHIFT  (25U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR153_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR153_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR154_MASK  (0x04000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR154_SHIFT  (26U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR154_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR154_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR155_MASK  (0x08000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR155_SHIFT  (27U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR155_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR155_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR156_MASK  (0x10000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR156_SHIFT  (28U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR156_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR156_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR157_MASK  (0x20000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR157_SHIFT  (29U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR157_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR157_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR158_MASK  (0x40000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR158_SHIFT  (30U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR158_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR158_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR159_MASK  (0x80000000U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR159_SHIFT  (31U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR159_RESETVAL  (0x00000001U)
#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_WKG_ENB_SECURE_FOR_INTR159_MAX  (0x00000001U)

#define CSL_WUGENMPU_WKG_ENB_SECURE_E_1_RESETVAL                (0xffffffffU)

/* AUX_CORE_BOOT_0 */

#define CSL_WUGENMPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_MASK       (0xFFFFFFFFU)
#define CSL_WUGENMPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_SHIFT      (0U)
#define CSL_WUGENMPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_RESETVAL   (0x00000000U)
#define CSL_WUGENMPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_MAX        (0xffffffffU)

#define CSL_WUGENMPU_AUX_CORE_BOOT_0_RESETVAL                   (0x00000000U)

/* AUX_CORE_BOOT_1 */

#define CSL_WUGENMPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_MASK       (0xFFFFFFFFU)
#define CSL_WUGENMPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_SHIFT      (0U)
#define CSL_WUGENMPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_RESETVAL   (0x00000000U)
#define CSL_WUGENMPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_MAX        (0xffffffffU)

#define CSL_WUGENMPU_AUX_CORE_BOOT_1_RESETVAL                   (0x00000000U)

/* STM_HWEVENTS_INV */

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_MASK    (0x00000001U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_SHIFT   (0U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_MASK    (0x00000002U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_SHIFT   (1U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_MASK    (0x00000004U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_SHIFT   (2U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_MASK    (0x00000008U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_SHIFT   (3U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_MASK    (0x00000010U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_SHIFT   (4U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_MASK    (0x00000020U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_SHIFT   (5U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_MASK    (0x00000040U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_SHIFT   (6U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_MASK    (0x00000080U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_SHIFT   (7U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_MASK    (0x00000100U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_SHIFT   (8U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_MASK    (0x00000200U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_SHIFT   (9U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_MAX     (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_MASK   (0x00000400U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_SHIFT  (10U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_MASK   (0x00000800U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_SHIFT  (11U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_MASK   (0x00001000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_SHIFT  (12U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_MASK   (0x00002000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_SHIFT  (13U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_MASK   (0x00004000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_SHIFT  (14U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_MASK   (0x00008000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_SHIFT  (15U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_MASK   (0x00010000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_SHIFT  (16U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_MASK   (0x00020000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_SHIFT  (17U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_MASK   (0x00040000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_SHIFT  (18U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_MASK   (0x00080000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_SHIFT  (19U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_MASK   (0x00100000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_SHIFT  (20U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_MASK   (0x00200000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_SHIFT  (21U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_MASK   (0x00400000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_SHIFT  (22U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_MASK   (0x00800000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_SHIFT  (23U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_MASK   (0x01000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_SHIFT  (24U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_MASK   (0x02000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_SHIFT  (25U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_MASK   (0x04000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_SHIFT  (26U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_MASK   (0x08000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_SHIFT  (27U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_MASK   (0x10000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_SHIFT  (28U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_MASK   (0x20000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_SHIFT  (29U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_MASK   (0x40000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_SHIFT  (30U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_MASK   (0x80000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_SHIFT  (31U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_RESETVAL  (0x00000000U)
#define CSL_WUGENMPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_MAX    (0x00000001U)

#define CSL_WUGENMPU_STM_HWEVENTS_INV_RESETVAL                  (0x00000000U)

/* AMBA_IF_MODE */

#define CSL_WUGENMPU_AMBA_IF_MODE_SBD_MASK                      (0x00000001U)
#define CSL_WUGENMPU_AMBA_IF_MODE_SBD_SHIFT                     (0U)
#define CSL_WUGENMPU_AMBA_IF_MODE_SBD_RESETVAL                  (0x00000001U)
#define CSL_WUGENMPU_AMBA_IF_MODE_SBD_MAX                       (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_BCM_MASK                      (0x00000002U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BCM_SHIFT                     (1U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BCM_RESETVAL                  (0x00000000U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BCM_MAX                       (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_BO_MASK                       (0x00000004U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BO_SHIFT                      (2U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BO_RESETVAL                   (0x00000000U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BO_MAX                        (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_BI_MASK                       (0x00000008U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BI_SHIFT                      (3U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BI_RESETVAL                   (0x00000000U)
#define CSL_WUGENMPU_AMBA_IF_MODE_BI_MAX                        (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_APB_FENCE_EN_MASK             (0x00000010U)
#define CSL_WUGENMPU_AMBA_IF_MODE_APB_FENCE_EN_SHIFT            (4U)
#define CSL_WUGENMPU_AMBA_IF_MODE_APB_FENCE_EN_RESETVAL         (0x00000001U)
#define CSL_WUGENMPU_AMBA_IF_MODE_APB_FENCE_EN_MAX              (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_ES2_PM_MODE_MASK              (0x00000020U)
#define CSL_WUGENMPU_AMBA_IF_MODE_ES2_PM_MODE_SHIFT             (5U)
#define CSL_WUGENMPU_AMBA_IF_MODE_ES2_PM_MODE_RESETVAL          (0x00000000U)
#define CSL_WUGENMPU_AMBA_IF_MODE_ES2_PM_MODE_MAX               (0x00000001U)

#define CSL_WUGENMPU_AMBA_IF_MODE_RESETVAL                      (0x00000011U)

/* PTMSYNCREQ_MASK */

#define CSL_WUGENMPU_PTMSYNCREQ_MASK_RESETVAL                   (0x00000000U)

/* PTMSYNCREQ_EN */

#define CSL_WUGENMPU_PTMSYNCREQ_EN_RESETVAL                     (0x00000000U)

/* TIMESTAMPCYCLELO */

#define CSL_WUGENMPU_TIMESTAMPCYCLELO_COUNTER_31_0_MASK         (0xFFFFFFFFU)
#define CSL_WUGENMPU_TIMESTAMPCYCLELO_COUNTER_31_0_SHIFT        (0U)
#define CSL_WUGENMPU_TIMESTAMPCYCLELO_COUNTER_31_0_RESETVAL     (0x00000000U)
#define CSL_WUGENMPU_TIMESTAMPCYCLELO_COUNTER_31_0_MAX          (0xffffffffU)

#define CSL_WUGENMPU_TIMESTAMPCYCLELO_RESETVAL                  (0x00000000U)

/* TIMESTAMPCYCLEHI */

#define CSL_WUGENMPU_TIMESTAMPCYCLEHI_COUNTER_47_32_MASK        (0x0000FFFFU)
#define CSL_WUGENMPU_TIMESTAMPCYCLEHI_COUNTER_47_32_SHIFT       (0U)
#define CSL_WUGENMPU_TIMESTAMPCYCLEHI_COUNTER_47_32_RESETVAL    (0x00000000U)
#define CSL_WUGENMPU_TIMESTAMPCYCLEHI_COUNTER_47_32_MAX         (0x0000ffffU)

#define CSL_WUGENMPU_TIMESTAMPCYCLEHI_RESETVAL                  (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
